AMD today shared its ideas for extending the x86 via the 128-Bit SSE5 Instruction Set. The SSE5 or Streaming SIMD (Single Instruction, Multiple Data) Extension instruction set allows for special instruction that can operate on multiple pieces of data at one time.
They plan to start include this beginning with the "Bulldozer" core that will be available in 2009. The reason for sharing this so early is to foster a dialog and solicit feedback, much the same way they shared the "Pacifica" instructions which went on to become AMD64.
In an interview with Dr. Dobbs they have a number of key wins such as a 5x performance increase in encryption operations using AES, and a 30% increase in algorithms that used floating-point matrix multiply.
AMD has thrived on innovation, but has struggled as of late in maintaining a performance advantage over Intel. Is this part of the long term strategy to right the AMD ship? Has Intel bought into this, or will the community forces its hand in adoption? Will publishing this so early allow Intel to just pull an EM64T with SSE5 and ultimately use it to its own advantage? Is this even something that community is really in need of like it was with AMD64 that has allowed for an elegant transition from x86 to x64 and relief from memory limitations?
What are your thoughts?
Posted
Aug 30 2007, 10:09 PM
by
Josh Phillips
Follow Me on Twitter
Did you enjoy this article? If yes, then subscribe to our
or
